Interconnection Networks for High-Performance Parallel Systems

Interconnection networks are a key element in High-Performance Computing (HPC) Clusters and Datacenters in the Exascale and Big-Data Era. They must offer high communication bandwidth and low latency to cope with the requirements of Applications, in order not to be the bottleneck of the entire HPC system. Actually, the path for designing the future interconnect technology has to face challenges like scalability, efficiency, heterogeneity, resiliency, virtualization, cost and power consumption.

The RAAP group has been carrying research in interconnection networks for more than 15 years, achieving significant insights which have been published in relevant conferences and journals, and incorporated to commercial products as well.

Topics:

Relevant Publications:

• • Jesús Escudero-Sahuquillo, Ernst Gunnar Gran, Pedro Javier García, Jose Flich, Tor Skeie, Olav Lysne, Francisco J. Quiles, José Duato.
    Efficient and Cost-Effective Hybrid Congestion Control for HPC Interconnection Networks.
    IEEE Trans. Parallel Distrib. Syst. 26(1): 107-119 (2015)

• • Francisco J. Andujar-Munoz, Juan A. Villar-Ortiz, José L. Sánchez, Francisco José Alfaro, José Duato.
    N-Dimensional Twin Torus Topology.
    IEEE Trans. Computers 64(10): 2847-2861 (2015)

• • Francisco J. Andujar, Juan A. Villar, José L. Sánchez, Francisco J. Alfaro, José Duato.
    Building 3D Torus Using Low-Profile Expansion Cards.
    IEEE Trans. Computers 63(11): 2701-2715 (2014)

• Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, Jose Flich, José Duato.
  An Effective and Feasible Congestion Management Technique for High-Performance MINs with Tag-Based Distributed Routing.
  IEEE Trans. Parallel Distrib. Syst. 24(10): 1918-1929 (2013)

Relevant Projects:

• Increasing on-chip network efficiency for improving the performance of chip multiprocessors supporting simultaneous parallel applications (2014-2017).
  We propose new techniques to improve network performance, thereby also improving the performance of individual applications when they simultaneously run in chip multiprocessors.
• Techniques to improve the architecture of servers, applications and services.
  We develop research on chip-multicore architecture and on-chip networks, aiming at increasing performance, reducing power consumption, increasing reliability by means of providing fault-tolerance support, increasing flexibility through virtualization techniques, and reducing silicon area.

People:

	Francisco J. Quiles, PhD Head of the group Full Professor Phone number: +34 967 599 200 – Ext. 2466 Email: Francisco.Quiles@uclm.es
	Jose Luis Sanchez, PhD Full Professor Phone number: +34 967 599 200 – Ext. 2439 Email: Jose.SGarcia@uclm.es
	Francisco J. Alfaro, PhD Associate Professor Phone number: +34 967 599 200 – Ext. 2490 Email: Fco.Alfaro@uclm.es
	Pedro Javier Garcia, PhD Assistant Professor Phone number: +34 967 599 200 – Ext. 2484 Email: PedroJavier.Garcia@uclm.es
	Jesus Escudero-Sahuquillo, PhD PostDoc Researcher Phone number: +34 967 599 200 – Ext. 2661 Email: Jesus.Escudero@uclm.es
	Juan A. Villar, PhD Research Assistant Phone number: +34 967 599 200 – Ext. 2662 Email: Juanantonio.Villar@uclm.es
	Francisco J. Andujar-Muñoz, PhD Research Assistant Phone number: +34 967 599 200 – Ext. 2784 Email: Franciscoj.Andujar@uclm.es
	Pedro Yebenes-Segura Research Assistant Phone number: +34 967 599 200 – Ext. 2641 Email: Pedro.Yebenes@uclm.es
	German Maglione-Mathey PhD student Phone number: +34 967 599 200 – Ext. 2657 Email: german.maglione@dsi.uclm.es
	Javier Cano PhD student Phone number: +34 967 599 200 – Ext. 2648 Email: javier.cano@uclm.es
	Juan-Jose Garcia-Castro PhD student Phone number: +34 967 599 200 – Ext. 2647 Email: juanjose.gcrespo@uclm.es
	José Manuel Rocher González PhD student Phone number: +34 967 599 200 – Ext. 2664 Email: JoseManuel.Rocher@uclm.es Research: Interconnection networks for High-Performance Parallel Systems